View WM8569SEDSV_755875.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w
DESCRIPTION
The WM8569 is a stereo audio codec ideal for DVD, PVR, LCD-TV and automotive applications. Independent ADC and DAC clocking permits separate record and playback sampling rates. A stereo 24-bit multi-bit sigma delta DAC with oversampling and digital interpolation filters provides the output signal. Digital audio input word lengths from 16-24 bits and sampling rates from 8kHz to 192kHz are supported. A stereo 24-bit multi-bit sigma delta ADC is used. Digital audio output word lengths from 16-24 bits and sampling rates from 32kHz to 96kHz are supported. The DAC and ADC support independent sampling rates. The audio data interface supports I2S, left justified, right justified and DSP digital audio formats. The device is controlled via a 3-wire serial interface. The interface provides access to all features including volume controls, mutes, de-emphasis and power management facilities. A hardware control interface allows access to a limited feature set. The WM8569 is available in a 28-lead SSOP.
WM8569
24-bit, 192kHz Stereo CODEC with Volume Control
FEATURES
* Audio Performance - 103dB SNR (`A' weighted @ 48kHz) DAC - DAC Sampling Frequency: 8kHz - 192kHz - 100dB SNR (`A' weighted @ 48kHz) ADC - ADC Sampling Frequency: 32kHz - 96kHz Independent Sampling Rates for ADC and DAC 3-wire SPI Serial or Hardware Control Interface Audio Mute and De-Emphasis Functions Programmable Audio Data Interface Modes - 16/20/24/32 bit Word Lengths - I2S, Left, Right Justified or DSP 2.7V to 5.5V Analogue Supply 2.7V to 3.6V Digital Supply 28-lead SSOP Package
* * * *
* * *
APPLICATIONS
* * * * * DVD Recorder Personal Video Recorder PC Sound Card Automotive Audio LCD-TV
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/
Production Data, June 2006, Rev 4.0 Copyright 2006 Wolfson Microelectronics plc
WM8569 TABLE OF CONTENTS
Production Data
DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY ............................................................................................................ 7 MASTER CLOCK TIMING ............................................................................................. 8 DIGITAL AUDIO INTERFACE - MASTER MODE ......................................................... 8 DIGITAL AUDIO INTERFACE - SLAVE MODE .......................................................... 10 MPU INTERFACE TIMING .......................................................................................... 12
INTERNAL POWER ON RESET CIRCUIT ..........................................................13 DEVICE DESCRIPTION.......................................................................................14
INTRODUCTION ......................................................................................................... 14 AUDIO DATA SAMPLING RATES............................................................................... 14 HARDWARE CONTROL MODES ............................................................................... 15 DIGITAL AUDIO INTERFACE ..................................................................................... 17 POWERDOWN MODES ............................................................................................. 21 ZERO DETECT ........................................................................................................... 21 SOFTWARE CONTROL INTERFACE OPERATION................................................... 21 REGISTER MAP ......................................................................................................... 22 CONTROL INTERFACE REGISTERS ........................................................................ 23
DIGITAL FILTER CHARACTERISTICS ...............................................................30
DAC FILTER RESPONSES......................................................................................... 30 ADC FILTER RESPONSES......................................................................................... 31 ADC HIGH PASS FILTER ........................................................................................... 31 DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................... 31
APPLICATIONS INFORMATION .........................................................................33
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 33 RECOMMENDED EXTERNAL COMPONENTS VALUES ........................................... 33 SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS ................................... 34
PACKAGE DIMENSIONS ....................................................................................35 IMPORTANT NOTICE ..........................................................................................36
ADDRESS: .................................................................................................................. 36
w
PD Rev 4.0 June 2006 2
Production Data
WM8569
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE WM8569SEDS/V TEMPERATURE RANGE -25 to +85oC -25 to +85oC PACKAGE 28-lead SSOP (Pb-free) 28-lead SSOP (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PEAK SOLDERING TEMPERATURE 260oC 260oC
WM8569SEDS/RV
Note: Reel quantity = 2,000
w
PD Rev 4.0 June 2006 3
WM8569 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 NAME DACMCLK ADCBCLK DACBLCK ADCLRC DACLRC DVDD DGND DIN NC DOUT CSB/IDF SCLK/IWL SDIN/DM MUTE REFADC ADCVREFN DACVREFN DACVREFP VMID AINR AINL VOUTL VOUTR NC AGND AVDD MODE TYPE Digital Input Digital Input Digital Input/Output Digital Input/Output Digital Input/Output Supply Supply Digital input No Connect Digital output Digital input Digital input Digital input Digital input/output Analogue output Supply Supply Supply Analogue output Analogue input Analogue input Analogue output Analogue output No Connect Supply Supply Digital Input DESCRIPTION Master DAC clock: 256fs, 384fs, 512fs or 768fs ADC audio interface bit clock DAC audio interface bit clock ADC left/right word clock DAC left/right word clock Digital positive supply Digital ground DAC data input No Connect ADC data output Software Mode: Serial control interface latch signal Hardware Mode: Input audio data format Software Mode: Serial control interface clock Hardware Mode: Audio data input word length Software Mode: Serial control interface data Hardware Mode: De-emphasis selection DAC Zero Flag output or DAC mute input
Production Data
ADC reference buffer decoupling pin; 10uF external decoupling ADC negative reference supply DAC negative reference supply DAC positive reference supply Midrail divider decoupling pin; 10uF external decoupling ADC right input ADC left input DAC left output DAC right output No Connect Analogue negative supply and substrate connection Analogue positive supply Control format selection: 0 = Software mode 1 = Hardware mode Master ADC clock: 256fs, 384fs, 512fs or 768fs
28
ADCMCLK
Digital Input
Note: Digital input pins have Schmitt trigger input buffers.
w
PD Rev 4.0 June 2006 4
Production Data
WM8569
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs
1 1
MIN -0.3V -0.3V DGND -0.3V AGND -0.3V
MAX +5V +7V DVDD +0.3V AVDD +0.3V 37MHz
Voltage range analogue inputs Master Clock Frequency
Operating temperature range, TA Storage temperature after soldering Notes: 1. Analogue and digital grounds must always be within 0.3V of each other.
-25C -65C
+85C +150C
w
PD Rev 4.0 June 2006 5
WM8569 RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Ground Difference DGND to AGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD. SYMBOL DVDD AVDD, VREFP AGND, VREFN, DGND -0.3 TEST CONDITIONS MIN 2.7 2.7 0 0 +0.3 TYP MAX 3.6 5.5
Production Data
UNIT V V V V
ELECTRICAL CHARACTERISTICS
Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs. PARAMETER 0dBFs Full scale output voltage SNR (Note 1,2,4) SNR (Note 1,2,4) SNR (Note 1,2,4) SNR (Note 1,2,4) A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted @ fs = 192kHz A-weighted @ fs = 48kHz, AVDD = 3.3V A-weighted @ fs = 96kHz, AVDD = 3.3V DNR A-weighted, -60dB full scale input 1kHz, 0dB.Fs 1kHz Input, 0dB gain PSRR 1kHz 100mVp-p 20Hz to 20kHz 100mVp-p ADC Performance Input Signal Level (0dB) Input resistance Input capacitance SNR (Note 1,2,4) SNR (Note 1,2,4) SNR (Note 1,2,4) A-weighted, 0dB gain @ fs = 48kHz A-weighted, 0dB gain @ fs = 96kHz A-weighted, 0dB gain @ fs = 48kHz, AVDD = 3.3V A-weighted, 0dB gain @ fs = 96kHz, AVDD = 3.3V 1kHz, -1dBFs 1kHz Input 80 2.0 x REFADC/5 20 10 100 100 93 Vrms k pF dB dB dB 90 95 SYMBOL TEST CONDITIONS MIN TYP 1.0 x VREFP/5 103 102 101 99 MAX UNIT Vrms dB dB dB dB DAC Performance (Load = 10k, 50pF)
SNR (Note 1,2,4)
99
dB
Dynamic Range (Note 2,4) Total Harmonic Distortion (THD) Mute Attenuation DAC channel separation Power Supply Rejection Ratio
103 -90 100 100 50 45 -80
dB dB dB dB dB dB
SNR (Note 1,2,4)
93
dB
Total Harmonic Distortion (THD) ADC Channel Separation
-82 90
-72
dB dB
w
PD Rev 4.0 June 2006 6
Production Data Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs. PARAMETER Mute Attenuation Power Supply Rejection Ratio PSRR SYMBOL TEST CONDITIONS 1kHz Input, 0dB gain 1kHz 100mVpp 20Hz to 20kHz 100mVpp Digital Logic Levels (CMOS Levels) Input LOW level Input HIGH level Input leakage current Input capacitance Output LOW Output HIGH Analogue Reference Levels Reference voltage Potential divider resistance Supply Current Analogue supply current Digital supply current Notes: 1. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted. AVDD, VREFP = 5V DVDD = 3.3V TBD TBD VVMID RVMID VREFP to VMID and VMID to VREFN VREFP/2 - 50mV VREFP/2 50 VREFP/2 + 50mV VOL VOH IOL=1mA IOH= -1mA 0.9 x DVDD VIL VIH 0.7 x DVDD 0.2 5 0.1 x DVDD 1 0.3 x DVDD MIN TYP 90 50 45 MAX
WM8569
UNIT dB dB dB
V V A pF V V V k
mA mA
All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
3.
TERMINOLOGY
1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD (dB) - THD is a ratio, of the rms values, of Distortion/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
3. 4. 5. 6.
w
PD Rev 4.0 June 2006 7
WM8569
MASTER CLOCK TIMING
t MCLKL MCLK tMCLKH t MCLKY
Production Data
Figure 1 ADC and DAC Master Clock Timing Requirements Test Conditions o AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, AGND, DGND = 0V, TA = +25 C, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time MCLK Duty cycle Table 1 Master Clock Timing Requirements tMCLKH tMCLKL tMCLKY 11 11 28 40:60 60:40 ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL AUDIO INTERFACE - MASTER MODE
Figure 2 Audio Interface - Master Mode
w
PD Rev 4.0 June 2006 8
Production Data
WM8569
DACBCLK/ ADCBCLK (Output) DACLRC/ ADCLRC (Output) t
DL
t
DDA
DOUT
DIN t
DST
t
DHT
Figure 3 Digital Audio Data Timing - Master Mode Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER DACLRC/ADCLRC propagation delay from DACBCLK/ADCBCLK falling edge DOUT propagation delay from ADCBCLK falling edge DIN setup time to DACBCLK rising edge DIN hold time from DACBCLK rising edge SYMBOL tDL TEST CONDITIONS MIN 0 TYP MAX 10 UNIT ns
Audio Data Input Timing Information
tDDA tDST tDHT
0 10 10
10
ns ns ns
Table 2 Digital Audio Data Timing - Master Mode
w
PD Rev 4.0 June 2006 9
WM8569
DIGITAL AUDIO INTERFACE - SLAVE MODE
Production Data
Figure 4 Audio Interface - Slave Mode
Figure 5 Digital Audio Data Timing - Slave Mode
w
PD Rev 4.0 June 2006 10
Production Data
WM8569
Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER ADCBCLK/DACBCLK cycle time ADCBCLK/DACBCLK pulse width high ADCBCLK/DACBCLK pulse width low ADCLRC/DACLRC set-up time to ADCBCLK/DACBCLK rising edge ADCLRC/DACLRC hold time from ADCBCLK/DACBCLK rising edge DIN set-up time to DACBCLK rising edge DIN hold time from DACBCLK rising edge DOUT propagation delay from ADCBCLK falling edge SYMBOL tBCY tBCH tBCL tLRSU TEST CONDITIONS MIN 50 20 20 10 TYP MAX UNIT ns ns ns ns
Audio Data Input Timing Information
tLRH
10
ns
tDS tDH tDD
10 10 0 10
ns ns ns
Table 3 Digital Audio Data Timing - Slave Mode
w
PD Rev 4.0 June 2006 11
WM8569
MPU INTERFACE TIMING
Production Data
Figure 6 SPI Compatible Control Interface Input Timing
Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated PARAMETER SCLK/IWL rising edge to CSB/IDF rising edge SCLK/IWL pulse cycle time SCLK/IWL pulse width low SCLK/IWL pulse width high SDIN/DM to SCLK/IWL set-up time SCLK/IWL to SDIN/DM hold time CSB/IDF pulse width low CSB/IDF pulse width high CSB/IDF rising to SCLK/IWL rising SYMBOL tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS MIN 60 80 30 30 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns
Table 4 3-Wire SPI Compatible Control Interface Input Timing Information
w
PD Rev 4.0 June 2006 12
Production Data
WM8569
INTERNAL POWER ON RESET CIRCUIT
Figure 7 Internal Power on Reset Circuit Schematic The WM8569 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used reset the digital logic into a default state after power up. The POR circuit is powered from DVDD and monitors DVDD. It asserts PORB low if DVDD is below a minimum threshold.
Figure 8 Typical Power-Up Sequence Figure 8 shows a typical power-up sequence. When DVDD goes above the minimum threshold, Vpord, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When DVDD rises to Vpor_on, PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, PORB is asserted low whenever DVDD drops below the minimum threshold Vpor_off. SYMBOL Vpord Vpor_on Vpor_off MIN 0.3 1.3 1.3 TYP 0.5 1.7 1.7 MAX 0.8 2.0 2.0 UNIT V V V
Table 5 Typical POR Operation (typical values, not tested)
w
PD Rev 4.0 June 2006 13
WM8569 DEVICE DESCRIPTION
INTRODUCTION
Production Data
WM8569 is a complete 2-channel audio codec, including digital interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multi-bit sigma delta DAC with volume control and output smoothing filter. The device is implemented as a separate stereo DAC and a stereo ADC in a single package and controlled by a single 3-wire software or hardware interface. The DAC has its own data input DIN, DAC word clock DACLRC, DAC bit clock DACBCLK and DAC master clock DACMCLK while the stereo ADC has its own data output DOUT, word clock ADCLRC, bit clock ADCBCLK and ADC master clock ADCMCLK. This allows the ADC and DAC to operate independently. The Audio Interface may be configured to operate in either master or slave mode. In Slave mode DACLRC/ADCLRC and DACBCLK/ADCBCLK are all inputs. In Master mode DACLRC/ADCLRC and DACBCLK/ADCBCLK are all outputs. The DAC has its own digital volume control that is adjustable in 0.5dB steps. A zero cross detect circuit is provided. The digital volume control detects a transition through the zero point before updating the volume. This minimises audible clicks and `zipper' noise as the gain values change. Control of internal functionality of the device is by 3-wire serial or pin programmable control interface. Operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided for the DAC, for operation of both the ADC and DAC master clocks of 256fs, 384fs, 512fs and 768fs is provided. In Slave mode, selection between clock rates is automatically controlled. In master mode, the sample rate is set by control bits DACRATE and ADCRATE. Audio sample rates (fs) from less than 8kHz up to 192kHz are allowed for the DAC and from less than 32kHz up to 96kHz for the ADC, provided the appropriate master clock is input. The audio data interface supports right-justified, left-justified and I2S interface formats along with a highly flexible DSP serial port interface.
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master system clock can be applied directly through the ADC and DAC MCLK input pin(s) with no software configuration necessary. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC and DAC. The DAC master clock for WM8569 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (DACLRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The ADC master clock for WM8569 supports audio sampling rates from 256fs to 768fs, where fs is the audio sampling frequency (ADCLRC) typically 32kHz, 44.1kHz, 48kHz or 96kHz. The master clock is used to operate the digital filters and the noise shaping circuits. In Slave mode the WM8569 has a master clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 master clocks). If there is a greater than 32 clocks error the interface defaults to 768fs mode. The master clocks must be synchronised with LRC, although the WM8569 is tolerant of phase variations or jitter on this clock. Table 6 shows the typical master clock frequency inputs for the WM8569. The signal processing for the WM8569 typically operates at an oversampling rate of 128fs for both ADC and DAC. The exception to this for the DAC is for operation with a 128/192fs system clock, e.g. for 192kHz operation, when the oversampling rate is 64fs. For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs.
w
PD Rev 4.0 June 2006 14
Production Data SAMPLING RATE (DACLRC/ ADCLRC) 32kHz 44.1kHz 48kHz 96kHz 192kHz System Clock Frequency (MHz) 128fs
DAC only
WM8569
192fs
DAC only
256fs 8.192 11.2896 12.288 24.576
384fs 12.288 16.9340 18.432 36.864
512fs 16.384 22.5792 24.576
768fs 24.576 33.8688 36.864
4.096 5.6448 6.144 12.288 24.576
6.144 8.467 9.216 18.432 36.864
Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable
Table 6 System Clock Frequencies Versus Sampling Rate
HARDWARE CONTROL MODES
When the MODE pin is held high, the following hardware modes of operation are available. Note: When in hardware mode the ADC and DAC will only run in slave mode.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes, MUTE controls the selection of MUTE directly, and can be used to enable and disable the automute function. This pin becomes an output when left floating and indicates infinite ZERO detect (IZD) has been detected. DESCRIPTION 0 1 Floating Normal Operation Mute DAC channels Enable IZD, MUTE becomes an output to indicate when IZD occurs. L=IZD detected, H=IZD not detected.
Table 7 Mute and Automute Control Figure 9 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VMID with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024 or more input samples the outputs will be connected directly to VMID if IZD is set. When MUTE is deasserted, the output will restart immediately from the current input sample.
1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006
Figure 9 Application and Release of Soft Mute
w
PD Rev 4.0 June 2006 15
WM8569
Production Data The MUTE pin is an input to select mute or not mute. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. The automute function detects a series of ZERO value audio samples of 1024 samples long being applied to both channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR'd through a 10k resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert mute. If MUTE is tied low, AUTOMUTED is overridden and will not mute unless the IZD register bit is set. If MUTE is driven from a bi-directional source, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) and can be used to drive external mute circuits. AUTOMUTED will be removed as soon as any channel receives a non-ZERO input. A diagram showing how the various Mute modes interact is shown below.
IZD (Register Bit) AUTOMUTED (Internal Signal) 10k MUTE PIN SOFTMUTE (Internal Signal)
MUTE (Register Bit)
Figure 10 Control of MUTE Modes
INPUT FORMAT SELECTION
In hardware mode, CSB/IDF and SCLK/IWL become input controls for selection of input data format type and input data word length for both the ADC and DAC. CSB/IDF 0 0 1 1 Table 8 Input Format Selection Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that the left/right clocks (ADCLRC and DACLRC) are high for a minimum of 24 bit clocks (ADCBCLK and DACBCLK) and low for a minimum of 24 bit clocks. SCLK/IWL 0 1 0 1 INPUT DATA MODE 24-bit right justified 20-bit right justified 16-bit I2S 24-bit I S
2
DE-EMPHASIS CONTROL
In hardware mode, the SDIN/DM pin becomes an input control for selection of de-emphasis filtering to be applied. SDIN/DM 0 1 Table 9 De-emphasis Control DE-EMPHASIS Off On
w
PD Rev 4.0 June 2006 16
Production Data
WM8569
DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
The audio interface operates in either Slave or Master mode, selectable using the DACMS and ADCMS control bits. In both Master and Slave modes DIN is always an input to the WM8569 and DOUT is always an output. The default is Slave mode. In Slave mode, DACLRC, ADCLRC, DACBCLK and ADCBCLK are inputs to the WM8569 (Figure 11). DIN and DACLRC are sampled by the WM8569 on the rising edge of DACBCLK. ADC data is output on DOUT and changes on the falling edge of ADCBCLK. By setting the control bit DACBCP the polarity of DACBCLK may be reversed so that DIN is sampled on the falling edge of DACBCLK. By setting the control bit ADCBCP, the polarity of ADCBCLK may be reversed so that DOUT changes on the rising edge of ADCBCLK.
Figure 11 Slave Mode In Master mode, DACLRC, ADCLRC, DACBCLK and ADCBCLK are outputs from the WM8569 (Figure 12). DACLRC, ADCLRC, DACBCLK and ADCBCLK are generated by the WM8569. DIN is sampled by the WM8569 on the rising edge of DACBCLK so the controller must output DAC data that changes on the falling edge of DACBCLK. ADC data is output on DOUT and changes on the falling edge of ADCBCLK. By setting the control bit DACBCP the polarity of DACBCLK may be reversed so that DIN is sampled on the falling edge of DACBCLK. By setting the control bit ADCBCP, the polarity of ADCBCLK may be reversed so that DOUT changes on the rising edge of ADCBCLK.
Figure 12 Master Mode
w
PD Rev 4.0 June 2006 17
WM8569
AUDIO INTERFACE FORMATS
Production Data
Audio data is applied to the internal DAC filters or output from the ADC filters, via the Digital Audio Interface. 5 popular interface formats are supported: * * * * * Left Justified mode Right Justified mode I2S mode DSP Mode A DSP Mode B
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. In left justified, right justified and I2S modes, the digital audio interface receives DAC data on the DIN input and outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with DACLRC/ADCLRC indicating whether the left or right channel is present. DACLRC/ADCLRC is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes, the minimum number of BCLKs per LRC period is 2 times the selected word length. LRC must be high for a minimum of word length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on LRC is acceptable provided the above requirements are met. In DSP mode A or B, the DAC channels are time multiplexed onto DIN. LRC is used as a frame sync signal to identify the MSB of the first word. The minimum number of DACBCLKs per DACLRC period is 6 times the selected word length. Any mark to space ratio is acceptable on DACLRC provided the rising edge is correctly positioned. The ADC data may also be output in DSP mode A or B, with ADCLRC used as a frame sync to identify the MSB of the first word. The minimum number of ADCBCLKs per ADCLRC period is 2 times the selected word length if only the ADC is being operated.
LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN is sampled by the WM8569 on the first rising edge of DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge of BCLK. LRC is high during the left samples and low during the right samples (Figure 13).
1/fs
LEFT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK
RIGHT CHANNEL
DIN1/2/3/ DOUT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 13 Left Justified Mode Timing Diagram
w
PD Rev 4.0 June 2006 18
Production Data
WM8569
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of DIN is sampled by the WM8569 on the rising edge of DACBCLK preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of ADCBCLK. LRC are high during the left samples and low during the right samples (Figure 14).
1/fs
LEFT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK
RIGHT CHANNEL
DIN1/2/3/ DOUT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 14 Right Justified Mode Timing Diagram
I S MODE
In I2S mode, the MSB of DIN is sampled by the WM8569 on the second rising edge of DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the first falling edge of ADCBCLK following an ADCLRC transition and may be sampled on the rising edge of ADCBCLK. LRC are low during the left samples and high during the right samples.
2
1/fs
LEFT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK
1 BCLK 1 BCLK 3 n-2 n-1 n 1 2 3
RIGHT CHANNEL
DIN1/2/3/ DOUT
1
2
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 15 I2S Mode Timing Diagram
DSP MODE A
In DSP mode A, the MSB of DAC left channel data is sampled by the WM8569 on the second rising edge on DACBCLK following a DACLRC rising edge. DAC right channel follows DAC left channel (Figure 16).
Figure 16 DSP Mode A Timing Diagram - DAC Data Input
w
PD Rev 4.0 June 2006 19
WM8569
Production Data The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of ADCBCLK following a low to high ADCLRC transition and may be sampled on the rising edge of ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 17)
1 BCLK 1/fs 1 BCLK
ADCLRC
ADCBCLK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n-1
n
1
2
n-1
n
MSB
LSB
Input Word Length (IWL)
Figure 17 DSP Mode A Timing Diagram - ADC Data Output
DSP MODE B
In DSP mode B, the MSB of DAC left channel data is sampled by the WM8569 on the first DACBCLK rising edge following a DACLRC rising edge. (Figure 18).
Figure 18 DSP Mode B Timing Diagram - DAC Data Input The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of ADCBCLK as the low to high ADCLRC transition and may be sampled on the rising edge of ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 19).
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n-1
n
1
2
n-1
n
1
MSB
LSB
Input Word Length (IWL)
Figure 19 DSP Mode B Timing Diagram - ADC Data Output
w
PD Rev 4.0 June 2006 20
Production Data
WM8569
POWERDOWN MODES
The WM8569 has powerdown control bits allowing specific parts of the WM8569 to be powered off when not being used. Control bit ADCPD powers off the ADC. The three stereo DACs each have a separate powerdown control bit, DACPD[2:0] allowing individual stereo DACs to be powered off when not in use. Setting ADCPD and DACPD[2:0] will powerdown everything except the references VMID and REFADC. These may be powered down by setting PDWN. Setting PDWN will override all other powerdown control bits. It is recommended that the ADC and DACs are powered down before setting PDWN.
ZERO DETECT
The WM8569 has a zero detect circuit for each DAC channel that detects when 1024 consecutive zero samples have been input. The MUTE pin output may be programmed to output the zero detect signal which may then be used to control external muting circuits. A `1' on MUTE indicates a zero detect. The zero detect may also be used to automatically enable DAC mute by setting IZD.
SOFTWARE CONTROL INTERFACE OPERATION
The WM8569 is controlled using a 3-wire serial interface in software mode or pin programmable in hardware mode. The control mode is selected by the state of the MODE pin.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
SDIN/DM is used for the program data, SCLK/IWL is used to clock in the program data and CSB/IDF is used to latch the program data. SDIN/DM is sampled on the rising edge of SCLK/IWL. The 3-wire interface protocol is shown in Figure 20.
Figure 20 3-Wire SPI Compatible Interface Notes: 1. 2. 3. B[15:9] are Control Address Bits B[8:0] are Control Data Bits CSB/IDF is edge sensitive - the data is latched on the rising edge of CSB/IDF.
w
PD Rev 4.0 June 2006 21
WM8569
REGISTER MAP
Production Data
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8569 can be configured using the Control Interface. All unused bits should be set to `0'.
REGISTER R0(00h) R1(01h) R2(02h) R3(03h) R8(08h) R9(09h) R10(0Ah) R11(0Bh) B15 B14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B13 0 0 0 0 0 0 0 0 B12 0 0 0 0 1 1 1 1 B11 0 0 0 0 0 0 0 0 B10 0 0 1 1 0 0 1 1 B9 0 1 0 1 0 1 0 1 ADC OSR 0 0 0 UPDATE 0 0 DEEMP 0 DACMS 0 B8 UPDATE UPDATE PL[8:5] PHASE B7 B6 B5 B4 B3 LDA[7:0] RDA[7:0] IZD DACIWL[5:4] ATC
DACBCP
B2
B1
B0
DEFAULT 011111111 011111111
0
DACLRP
0
0
100100000 000000000 011111111
DACFMT[1:0]
MASTDA[7:0] 0 PWRDNALL ADCMS DMUTE
0 0 0 0 ZCD ADCPD
000000000 010000000 001000000
DACRATE[8:6]
DACPD
ADCRATE[7:5]
ADCIWL[3:2] AMUTE ALL
ADCFMT[1:0]
R12(0Ch)
0
0
0
1
1
0
0
MPD
ADCBCP
ADCLRP RESET
ADCHP
AMUTEL AMUTER
000000000 000000000
R31(1Fh)
0
0
1
1
1
1
1
w
PD Rev 4.0 June 2006 22
Production Data
WM8569
CONTROL INTERFACE REGISTERS
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both the left and right channel of the DAC from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS 0000010 DAC Channel Control BIT 3 LABEL ATC DEFAULT 0 DESCRIPTION Attenuator Control Mode: 0: Right channel use right attenuations 1: Right channel use left attenuations
INFINITE ZERO DETECT ENABLE
Setting the IZD register bit will enable the internal infinite zero detect function: REGISTER ADDRESS 0000010 DAC Channel Control BIT 4 LABEL IZD DEFAULT 0 DESCRIPTION Infinite Zero Mute Enable 0 : Disable inifinite zero mute 1: Enable infinite zero mute
With IZD enabled, applying 1024 consecutive zero input samples each stereo channel will cause that stereo channel outputs to be muted to VMID. Mute will be removed as soon as that stereo channel receives a non-zero input.
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right input to the audio Interface are applied to the left and right DAC: REGISTER ADDRESS 0000010 DAC Control BIT 8:5 LABEL PL[3:0] DEFAULT 1001 PL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DESCRIPTION Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Mute Mute Mute Mute Left Left Left Left Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2
w
PD Rev 4.0 June 2006 23
WM8569
DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the DACFMT[1:0] register bits: REGISTER ADDRESS 0000011 Interface Control BIT 1:0 LABEL DACFMT [1:0] DEFAULT 00
Production Data
DESCRIPTION Interface Format Select: 00 : Right justified mode 01: Left justified mode 10: I2S mode 11: DSP mode A orB
In left justified, right justified or I2S modes, the DACLRP register bit controls the polarity of DACLRC. If this bit is set high, the expected polarity of DACLRC will be the opposite of that shown Figure 13, Figure 14 and Figure 15. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the DACLRP register bit is used to select between modes A and B. REGISTER ADDRESS 0000011 Interface Control BIT 2 LABEL DACLRP DEFAULT 0 DESCRIPTION In left/right/I2S Modes: DACLRC Polarity (normal) 0 : Normal DACLRC polarity 1: Inverted DACLRC polarity In DSP Mode: 0 : Mode A 1: Mode B By default, DACLRC and DIN are sampled on the rising edge of DACBCLK and should ideally change on the falling edge. Data sources that change DACLRC and DIN on the rising edge of DACBCLK can be supported by setting the DACBCP register bit. Setting DACBCP to 1 inverts the polarity of DACBCLK to the inverse of that shown in Figure 13 to Figure 19. REGISTER ADDRESS 0000011 Interface Control BIT 3 LABEL DACBCP DEFAULT 0 DESCRIPTION DACBCLK Polarity (DSP Modes): 0: Normal BCLK polarity 1: Inverted BCLK polarity
The DACIWL[1:0] bits are used to control the input word length. REGISTER ADDRESS 0000011 Interface Control BIT 5:4 LABEL DACIWL [1:0] DEFAULT 00 DESCRIPTION Input Word Length: 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data
Note: 32-bit right justified mode is not supported. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8569 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. Note: In 24 bit I S mode, any width of 24 bits or less is supported provided that LRC is high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs. A number of options are available to control how data from the Digital Audio Interface is applied to the DAC channels.
2
w
PD Rev 4.0 June 2006 24
Production Data
WM8569
DAC OUTPUT PHASE
The DAC Phase control word determines whether the output of the DAC is non-inverted or inverted REGISTER ADDRESS 0000011 DAC Phase BIT 6 LABEL PHASE DEFAULT 0 DESCRIPTION 0 = non-inverted 1 = inverted
DIGITAL ZERO CROSS-DETECT
The Digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This is enabled by control bit ZCD. REGISTER ADDRESS 0001001 DAC Control BIT 0 LABEL ZCD DEFAULT 0 DESCRIPTION DAC Digital Volume Zero Cross Disable: 0: Zero cross detect enabled 1: Zero cross detect disabled
DAC MUTE MODES
The WM8569 has a mute for the DAC channels. Setting MUTE will apply a `soft' mute to the input of the digital filters. REGISTER ADDRESS 0001001 DAC Mute BIT 3 LABEL DMUTE DEFAULT 0 DESCRIPTION DAC Soft Mute Select 0 = Not mute 1 = Mute
Refer to Figure 9 for the plot of application and release of soft mute. Note that all other means of muting the DAC channels: setting the PL[3:0] bits to 0, setting the PDWN bit or setting attenuation to 0 will cause much more abrupt muting of the output.
ADC MUTE MODES
Each ADC channel also has a mute control bit, which mutes the inputs to the ADC. REGISTER ADDRESS 0001100 ADC Mute BIT 0 LABEL AMUTER DEFAULT 0 DESCRIPTION ADC Mute Select: 0 : Normal operation 1: mute ADC right ADC Mute Select: 0 : Normal operation 1: mute ADC left ADC Mute Select: 0 : Normal operation 1: mute both ADC channels
1
AMUTEL
0
2
AMUTEALL
0
DE-EMPHASIS MODE
Each stereo DAC channel has an individual de-emphasis control bit: REGISTER ADDRESS 0001001 DAC De-Emphahsis Control BIT 6 LABEL DEEMPH DEFAULT 0 DESCRIPTION De-emphasis Channel Selection Select: 0 = Not de-emphasis 1 = De-emphasis PD Rev 4.0 June 2006 25
w
WM8569
POWERDOWN MODE AND ADC/DAC DISABLE
Production Data
The ADC and DAC may be powered down individually by setting the ADCPD and DACPD disable bits. Setting ADCPD will disable the ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when ADCPD is unset. Setting DACPD will disable the DAC and select a low power mode. REGISTER ADDRESS 0001010 Powerdown Control BIT 0 LABEL ADCPD DEFAULT 0 DESCRIPTION ADC Disable: 0: Active 1: Disable DAC Disable
1
DACPD
0
MASTER POWERDOWN
This control bit powers down the references for the whole chip. Therefore for complete powerdown, both the ADC and DACs should be powered down first before setting this bit. REGISTER ADDRESS 0001010 Interface Control BIT 4 LABEL PWRDNALL DEFAULT 0 DESCRIPTION Master Power Down Bit: 0: Not powered down 1: Powered down
DAC MASTER MODE SELECT
Control bit DACMS selects between audio interface Master and Slave Modes. In Master mode, DACLRC and DACBCLK are outputs and are generated by the WM8569. In Slave mode DACLRC and DACBCLK are inputs to WM8569. REGISTER ADDRESS 0001010 Interface Control BIT 5 LABEL DACMS DEFAULT 0 DESCRIPTION DAC Audio Interface Master/Slave Mode Select: 0: Slave mode 1: Master mode
MASTER MODE DACLRC FREQUENCY SELECT
In Master mode the WM8569 generates DACLRC and DACBCLK. These clocks are derived from the master clock and the ratio of DACMCLK to DACLRC is set by DACRATE. REGISTER ADDRESS 0001010 Interface Control BIT 8:6 LABEL DACRATE [2:0] DEFAULT 010 DESCRIPTION Master Mode MCLK:LRC Ratio Select: 000: 128fs (DAC only) 001: 192fs (DAC only) 010: 256fs 011: 384fs 100: 512fs 101: 768fs
w
PD Rev 4.0 June 2006 26
Production Data
WM8569
ADC DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the ADCFMT[1:0] register bits: REGISTER ADDRESS 0001011 Interface Control BIT 1:0 LABEL ADCFMT[1:0] DEFAULT 00 DESCRIPTION Interface Format Select 00: Right justified mode 01: Left justified mode 10: I2S mode 11: DSP mode A or B
The ADCIWL[1:0] bits are used to control the input word length. REGISTER ADDRESS 0001011 Interface Control BIT 3:2 LABEL ADCIWL[1:0] DEFAULT 00 DESCRIPTION Input Word Length 00: 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data
Note: 32-bit right justified mode is not supported. In all modes, the data is signed 2's complement.
ADC MASTER MODE SELECT
Control bit ADCMS selects between audio interface Master and Slave Modes. In Master mode ADCLRC and ADCBCLK are outputs and are generated by the WM8569. In Slave mode ADCLRC and ADCBCLK are inputs to WM8569. REGISTER ADDRESS 0001011 Interface Control BIT 4 LABEL ADCMS DEFAULT 0 DESCRIPTION ADC Audio Interface Master/Slave Mode Select: 0: Slave mode 1: Master mode
MASTER MODE ADCLRC FREQUENCY SELECT
In Master mode the WM8569 generates ADCLRC and ADCBCLK. These clocks are derived from the master clock and the ratio of ADCMCLK to ADCLRC is set by ADCRATE. REGISTER ADDRESS 0001011 ADCLRC and ADCBCLK Frequency Select BIT 7:5 LABEL ADCRATE [2:0] DEFAULT 010 DESCRIPTION Master Mode ADCMCLK:ADCLRC Ratio Select: 010: 256fs 011: 384fs 100: 512fs 101: 768fs
ADC OVERSAMPLING RATE SELECT
For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversampling rate to 64fs. The 64fs oversampling rate is only available in modes were a 96KHz rate is supported, i.e. 256fs or 384fs. In all other modes the ADC will stay in a 128fs oversampling rate irrespective of what this bit is set to. REGISTER ADDRESS 0001011 ADC Oversampling Rate BIT 8 LABEL ADCOSR DEFAULT 0 DESCRIPTION ADC Oversampling Rate Select: 0: 128x oversampling 1: 64x oversampling
w
PD Rev 4.0 June 2006 27
WM8569
ADC HIGHPASS FILTER DISABLE
Production Data
The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled using software control bit ADCHPD. REGISTER ADDRESS 0001100 ADC Control BIT 3 LABEL ADCHPD DEFAULT 0 DESCRIPTION ADC Highpass Filter Disable: 0: Highpass filter enabled 1: Highpass filter disabled
In left justified, right justified or I S modes, the ADCLRP register bit controls the polarity of ADCLRC. If this bit is set high, the expected polarity of ADCLRC will be the opposite of that shown in Figure 13, Figure 14 and Figure 15. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the ADCLRP register bit is used to select between modes A and B. REGISTER ADDRESS 0001100 Interface Control BIT 4 LABEL ADCLRP DEFAULT 0 DESCRIPTION In Left/Right/I2S Modes: ADCLRC Polarity (normal) 0: normal DACLRC polarity 1: inverted DACLRC polarity In DSP Mode: 0: DSP mode A 1: DSP mode B
2
By default, ADCLRC and DOUT are sampled on the rising edge of ADCBCLK and should ideally change on the falling edge. Data sources that change ADCLRC and DOUT on the rising edge of ADCBCLK can be supported by setting the ADCBCP register bit. Setting ADCBCP to 1 inverts the polarity of ADCBCLK to the inverse of that shown in Figure 13 to Figure 19 REGISTER ADDRESS 0001100 Interface Control BIT 5 LABEL ADCBCP DEFAULT 0 DESCRIPTION ADCBCLK Polarity (DSP Modes): 0: normal BCLK polarity 1: inverted BCLK polarity
MUTE PIN DECODE
The MUTE pin can either be used an output or an input. As an output it indicated 1024 consecutive zero samples to the DAC. By default selecting the MUTE to represent if the DAC has received more than 1024 midrail samples will cause the MUTE to be asserted as a softmute on the DAC. Disabling the decode block will cause any logical high on the MUTE pin to apply a softmute to the DAC.
REGISTER ADDRESS 0001100 ADC Control
BIT 6
LABEL MPD
DEFAULT 0
DESCRIPTION MUTE Pin Decode Disable: 0: MUTE pin decode enable 1: MUTE pin decode disable
w
PD Rev 4.0 June 2006 28
Production Data
WM8569
DAC DIGITAL VOLUME CONTROL
The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers
REGISTER ADDRESS 0000000 Digital Attenuation DACL 0000001 Digital Attenuation DACR
BIT 7:0 8
LABEL LDA[7:0] UPDATE
DEFAULT 11111111 (0dB) Not latched
DESCRIPTION Digital Attenuation data for Left channel DACL in 0.5dB steps. See Table 10 Controls simultaneous update of all Attenuation Latches 0: Store LDA in intermediate latch (no change to output) 1: Store LDA and update attenuation on all channels Digital Attenuation data for Right channel DACR in 0.5dB steps. See Table 10 Controls simultaneous update of all Attenuation Latches 0: Store RDA in intermediate latch (no change to output) 1: Store RDA and update attenuation on all channels. Digital Attenuation data for all DAC channels in 0.5dB steps. See Table 10 Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels.
7:0 8
RDA[6:0] UPDATE
11111111 (0dB) Not latched
0001000 Master Digital Attenuation (all channels)
7:0 8
MASTDA [7:0] UPDATE
11111111 (0dB) Not latched
L/RDAX[7:0] 00(hex) 01(hex) : : : FE(hex) FF(hex)
ATTENUATION LEVEL - dB (mute) -127dB : : : -0.5dB 0dB
Table 10 Digital Volume Control Attenuation Levels
SOFTWARE REGISTER RESET
Writing to register 11111 will cause a register reset, resetting all register bits to their default values. The device will be held in this reset state until a subsequent register write to any address is completed.
w
PD Rev 4.0 June 2006 29
WM8569 DIGITAL FILTER CHARACTERISTICS
PARAMETER Passband Passband ripple Stopband Stopband Attenuation Passband Passband ripple Stopband Stopband Attenuation Table 11 Digital Filter Characteristics f > 0.555fs 0.555fs -60 dB f > 0.5465fs DAC Filter 0.05 dB -3dB 0.487fs 0.05 dB 0.444fs 0.5465fs -65 dB TEST CONDITIONS ADC Filter 0.01 dB -6dB 0 0.5fs 0.01 dB 0.4535fs MIN TYP MAX UNIT
Production Data
DAC FILTER RESPONSES
0.2 0 0.15 -20 0.1
Response (dB)
Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-100
-0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
-120
Figure 21 DAC Digital Filter Frequency Response - 44.1, 48 and 96kHz
Figure 22 DAC Digital Filter Ripple -44.1, 48 and 96kHz
0.2 0 0 -20
Response (dB)
Response (dB)
-0.2
-40
-0.4
-60
-0.6
-0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 23 DAC Digital Filter Frequency Response - 192kHz
Figure 24 DAC Digital Filter Ripple - 192kHz
w
PD Rev 4.0 June 2006 30
Production Data
WM8569
0.02
ADC FILTER RESPONSES
0 0.015 0.01 -20
Response (dB)
Response (dB)
0.005 0 -0.005 -0.01 -0.015 -0.02
-40
-60
-80
0
0.5
1
1.5 Frequency (Fs)
2
2.5
3
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (Fs)
0.35
0.4
0.45
0.5
Figure 25 ADC Digital Filter Frequency Response
Figure 26 ADC Digital Filter Ripple
ADC HIGH PASS FILTER
The WM8569 has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial.
H ( z) =
1 - z -1 1 - 0.9995z -1
DIGITAL DE-EMPHASIS CHARACTERISTICS
0 1 0.5 -2 0
Response (dB)
-4
Response (dB)
-0.5 -1 -1.5 -2
-6
-8 -2.5 -10 0 2 4 6 8 10 Frequency (kHz) 12 14 16 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16
Figure 27 De-Emphasis Frequency Response (32kHz)
Figure 28 De-Emphasis Error (32kHz)
w
PD Rev 4.0 June 2006 31
WM8569
0 0.4 0.3 -2 0.2
Response (dB)
Response (dB)
Production Data
-4
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20
Figure 29 De-Emphasis Frequency Response (44.1kHz)
0
Figure 30 De-Emphasis Error (44.1kHz)
1 0.8
-2
0.6 0.4
Response (dB)
-4
Response (dB)
0.2 0 -0.2 -0.4
-6
-8
-0.6 -0.8
-10 0 5 10 15 Frequency (kHz) 20
-1 0 5 10 15 Frequency (kHz) 20
Figure 31 De-Emphasis Frequency Response (48kHz)
Figure 32 De-Emphasis Error (48kHz)
w
PD Rev 4.0 June 2006 32
Production Data
WM8569
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 33 Recommended External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 and C5 C2 to C4 C8 and C9 C6 and C10 C7 and C11 C12 R1 SUGGESTED VALUE 10F 0.1F 1F 0.1F 10F 10F 33 Filtering for VREFP. Omit if AVDD low noise. Filtering for VREP. Use 0 if AVDD low noise. DESCRIPTION De-coupling for DVDD and AVDD. De-coupling for DVDD and AVDD. Analogue input high pass filter capacitors Reference de-coupling capacitors for VMID and ADCREF pin.
Table 12 Recommended External Components Description Note: Further details for filtering on reference pins are available in Wolfson Application Note WAN0144.
w
PD Rev 4.0 June 2006 33
WM8569
SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS
Production Data
It is recommended that a lowpass filter be applied to the output from each DAC channel for Hi Fi applications. Typically a second order filter is suitable and provides sufficient attenuation of high frequency components (the unique low order, high bit count multi-bit sigma delta DAC structure used in WM8569 produces much less high frequency output noise than normal sigma delta DACs. This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment. Wolfson Application Note WAN0171 provides details of suitable post-DAC filter circuits.
Figure 34 Recommended Post DAC Filter Circuit
w
PD Rev 4.0 June 2006 34
Production Data
WM8569
PACKAGE DIMENSIONS
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) DM007.E
b
28
e
15
E1
E
1
D
14
GAUGE PLANE
c A A2 A1
L
0.25
L1
-C0.10 C
SEATING PLANE
Symbols A A1 A2 b c D e E E1 L L1 REF: MIN ----0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.55 0
o
Dimensions (mm) NOM --------1.75 0.30 ----10.20 0.65 BSC 7.80 5.30 0.75 1.25 REF o 4 JEDEC.95, MO-150
MAX 2.0 0.25 1.85 0.38 0.25 10.50 8.20 5.60 0.95 8
o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
w
PD Rev 4.0 June 2006 35
WM8569 IMPORTANT NOTICE
Pre-Production
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
w
PD Rev 4.0 June 2006 36

▲Up To Search▲

Price & Availability of WM8569SEDSV

	To Download WM8569SEDSV Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .